As the demand for cheaper, faster, lower power consuming integrated circuits increases, so must the device packing density of the integrated circuit (IC). Minimizing transistor dimensions is of paramount importance to the advancement of semiconductor technologies. Minimizing transistor dimensions allows more transistors to be formed in a given area. Minimizing the dimensions also allows the transistors to operate at higher speeds. The ability to place more high speed transistors in an IC allows more complex and sophisticated functionality to be incorporated into the IC device. Therefore, as a result of reducing the size of transistors in an IC, and improving the speed of the IC, products which use these IC's, such as, for example, home computers, will be able to operate faster and with greater functionality than ever before.
Increasing the device packing density of an IC by minimizing transistor dimensions inherently requires that the interconnect technology used to couple transistors together be similarly minimized. In a typical interconnect technology scheme, after transistors are formed on a semiconductor substrate, a layer of dielectric material is used to coat the surface of the transistors to physically and electrically insulate them. Once this dielectric material is deposited, openings are etched through the dielectric material to the underlying semiconductor substrate. Conductive material is deposited into these openings in order to make electrical contact to the substrate surface. These openings filled with conductive material are called contacts.
Once a first layer of interconnects has been deposited on the surface of the first dielectric layer, a second dielectric layer is deposited to coat the surface of this first interconnect layer. Openings are then etched into this second dielectric layer to permit electrical coupling to the first interconnect layer by filling these openings with conductive material. These openings filled with conductive material are called vias. Once the interconnects of the second interconnect layer have been formed, a third dielectric layer is deposited to coat the second interconnect layer, and vias are again formed in the third dielectric layer. This process of forming an interconnect layer, coating with a dielectric layer, forming vias in the dielectric layer, and forming another interconnect layer on its surface may be repeated any number of times in IC manufacturing technology.
The dimensions of these contacts and vias have historically been limited by the photolithographic technology used to define the size and location of contact and via openings. For example, conventional photolithographic technologies are currently capable of defining, or "resolving", an opening having a minimum width of approximately 0.4-0.5 microns. This minimum resolvable dimension significantly limits the device packing density of the IC.
For example, since contact openings cannot be smaller than 0.4 microns, transistors cannot be spaced any closer than this minimum resolvable dimension or else the contact opening will be etched through a transistor, destroying it. Furthermore, since the accuracy in aligning a contact opening to an underlying semiconductor substrate region between two transistors is imprecise, transistors must be spaced far enough apart to account for any potential misalignment of the contact opening. In addition, some practitioners make contact openings wider than the minimum resolvable dimension because it is difficult to fill such small contact openings with conductive material. Therefore, to account for enlarged and misaligned contact openings, transistors may ultimately be spaced as far as 1 micron apart from each other, lowering the transistor packing density of the IC.
While more advanced and complex photolithographic technologies have been developed to resolve smaller dimensions, these advanced technologies are expensive, typically unreliable, and currently unmanufacturable. What is needed, then, is a manufacturable process whereby contacts and vias can be formed having widths less than the minimum resolvable dimension of the photolithographic technology employed to define the openings.